1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a system-in-package (SiP) technology.
2. Description of the Related Art
Various stack-type semiconductor devices and bonding methods therefor have been discussed.
As an example thereof, a technology for connecting a memory chip to a lead terminal of a lead frame is disclosed in each of JP 11-054693 A, JP 11-074451 A, and JP 2000-332194 A.
JP 11-054693 A and JP 11-074451 A each disclose a semiconductor device having a first semiconductor chip and a second semiconductor chip stacked in the stated order on an island. The first and second semiconductor chips are memory chips. The second semiconductor chip, which is slightly smaller than the first semiconductor chip, is mounted on a central portion of the first semiconductor chip, and two opposing sides of the first semiconductor chip are exposed from the second semiconductor chip. On each of the two opposing sides, first bonding pads are formed in an exposed portion from the opposing side to each side adjacent to the opposing side, along an outer periphery of the first semiconductor chip. Among the first bonding pads, bonding pads that are positioned on ends of the opposing side are wire bonded to lead terminals each facing the adjacent side.
JP 2000-332194 A discloses a multi-chip package having two small and large chips stacked on top of each other.
In the device disclosed in JP 11-054693 A, among the electrode pads formed on one side of the second semiconductor chip, an electrode pad positioned on an end of the one side is connected to a chip enable pin ICE/2 across the opposing side of the first semiconductor chip.
Further, a technology for mounting a chip on a wiring board is disclosed in each of JP 01-235264 A, JP 2005-317830 A, JP 2005-302871 A, and JP 2001-007278 A.
JP 01-235264 A discloses an example where a terminal to be bonded to a chip enable terminal CE of a printed wiring board is formed on a corner of a chip.
JP 2005-317830 A discloses a multi-chip package having a lower memory chip, an upper memory chip, and a CPU chip that are mounted in the stated order on an insulating substrate. In the package, the CPU chip has a rectangular shape, and pads are formed along each of four sides of the CPU chip. Further, substrate pads are formed on the insulating substrate along each side of the CPU chip. The pads of the CPU chip are bonded to electrode pads that are formed along one of the sides on which the pads of the CPU chip are formed.
JP 2005-302871 A discloses a stacked semiconductor device including a plurality of semiconductor devices that are stacked on top of each other to be displaced stepwise in a direction perpendicular to one side of a substrate. On a first substrate on which the semiconductor devices are to be mounted, lines of bonding pads corresponding to the number of semiconductor devices are formed. The semiconductor devices each have a structure in which a chip is flip-chip connected to the substrate. Bonding pads of the semiconductor device formed in a lowermost layer are connected to bonding pads positioned in a line formed closest to the semiconductor device, among the bonding pads of the first substrate. Among the bonding pads of the first substrate, the bonding pads of the semiconductor device formed in the upper layer are connected to the bonding pads farther apart from the semiconductor device.
Further, JP 2005-302871 A discloses a stacked semiconductor device in which a plurality of semiconductor devices are stacked to be displaced in an L shape along one side of the substrate.
JP 2001-007278 also discloses a stack-type multi-chip package. In the package, a wiring sheet is inserted between an upper chip and a lower chip, and bonding pads formed on a surface of the upper chip and a package substrate are connected to each other through a wiring pattern formed on the wiring sheet.
Incidentally, in recent years, an increase in capacity of a memory package is required. However, in a case of a conventional memory stack, when a plurality of chips are stacked on top of each other, the wires are prevented from being brought into contact with each other, with the result that an entire package area is increased.
For example, in the case of the structure disclosed in JP 2005-302871 A as described above, there are formed as many pad lines on the substrate as the number of semiconductor devices stacked on at least one side of each of the semiconductor devices constituting the stack. Accordingly, a pad forming region of the package substrate is large, so there is room for improvement in terms of reducing the size of the package.
Further, in the structure disclosed in 2005-302871 A, when the number of pad lines on the substrate is to be simply reduced, there is a fear that the arrangement of bonding wires are complicated and the wires are brought into contact with each other. Further, there is another fear that, in order to prevent the wires from being brought into contact with each other, the package is increased in size. Such points will be described below with reference to FIGS. 13 and 14.
FIG. 13 is a plan view showing a structure of a semiconductor device which has been discussed by the inventors of the present invention. FIG. 14 is a cross-sectional diagram of the semiconductor device taken along a direction in which the chips are displaced.
In a semiconductor device 200 shown in FIGS. 13 and 14, terminals, that is, electrode pads of the chips are each arranged on one side. The arrangement of the pads each functioning as a chip select (hereinafter, referred to as “CS”) terminal is not considered.
Specifically, on amounting board 201, a first memory chip 203a, a second memory chip 203b, and a third memory chip 203c are stacked in the stated order. Those memory chips are sealed with a sealing resin 205. On a back surface of the mounting board 201, bump electrodes 207 are formed.
The first memory chip 203a, the second memory chip 203b, and the third memory chip 203c have the same rectangular planar shape, and each include electrode pads arranged in a single line along one side of the rectangle. The chips are displaced stepwise to be stacked on top of each other so that an electrode pad forming region of each chip is exposed. Among the electrode pads formed on each chip, electrode pads each functioning as an address terminal or a data terminal are wire bonded to each other (for example, wire 217 and wire 219) between the chips.
Stitches of the mounting board 201 are arranged so as to be adjacent to the line of the electrode pads of the first memory chip 203a. In this case, stitches for terminals that can be used both for address and data are arranged in a single line so as to be adjacent to the electrode pad forming region of the first memory chip 203a, and stitches (stitches 211b and 211c) for chip select of each of the second memory chip 203b and the third memory chip 203c are further arranged outside the line of the stitches for terminals.
A CS pad 221a of the first memory chip 203a, a CS pad 221b of the second memory chip 203b, and a CS pad 221c of the third memory chip 203c are each directly wire bonded to the stitch 211a, the stitch 211b, and the stitch 211c of each chip, through a wire 231, a wire 233, and a wire 235.
Thus, on each memory chip, an address terminal or a data terminal and a CS terminal are formed for each chip, and the electrode pad functioning as the CS terminal cannot be bonded through the electrode pad of another chip. While the adjacent wires are taken into consideration, the CS terminal of each chip is directly wired to the stitch on the mounting board.
However, in a structure of a conventional semiconductor package of a memory stack type, arrangement of the electrode pads functioning as chip select terminals and a reduction in size of the entire package are not considered. As a result, as shown in FIG. 13, the wire connecting the chip select pad and the stitch on the board to each other strides over or intersects another wire in some areas, which complicates the wiring. Accordingly, it is necessary to sufficiently secure a space for preventing the wires from being brought into contact with each other, which becomes a cause of the increase in size of the package.
Further, in order to prevent the wires from intersecting each other, when a line of stitches is formed for each chip as disclosed in 2005-302871 A, it is necessary to provide a large space for forming the lines of the stitches on the mounting board, which results in the increase in size of the package.